基本結構（Basic Modelling）

一個基本的VHDL設計包含至少一個實體/結構體對。在大型的設計程序中，我們通常編寫許多個實體/結構體對，并把他們組合起來，來實現一個完成的電路。

Every VHDL design description consists of at least one entity/architecture pair. In a large design, you will typically write many entity/architecture pairs and connect them together to form a complete circuit.

實體（Entity）

一個實體（entity）定義用來描述電路與外部世界的聯系，它的輸入和輸出接口（端口（ports）和類屬（generics））。在原理圖設計中，實體定義就像是原理圖中的一個電路邏輯塊。

An entity declaration describes the circuit as it appears from the outside world, its input and output interfaces (ports and generics). In a schematic design, you might think of an entity declaration as being analogous to a block symbol on a schematic.一個實體定義為電路提供完整的接口。你可以使用實體提供的接口信息，將其連接到其他更高層的電路中。An entity declaration PRovides the complete interface for a circuit. You have all information you need to connect that circuit into other, higher-level circuits.

結構體（Architecture）

結構體（architecture）定義是一個最小VHDL設計中的第二部分。結構體描述了它所綁定的實體中，實際的功能或內容。你可以把結構體看作是，原理圖設計中，一個高層電路邏輯塊中的底層電路圖。

The architecture declaration is the second part of a minimal VHDL design. The architecture describes the actual function, or contents, of the entity to which the architecture is bound. In a schematic design you can think that an architecture is analogous to a lower-level schematic referenced by the higher-level functional block symbol.我們可以將許多子元件（sub-components）進行組合，來實現實體的具體功能。每一個子元件是許多實體的實例（instance），實例的接口通過信號（signals）連接在一起。一個信號代表一個電氣連接，可以是一根線或者總線。端口映射（port map）用來連接信號和實例的端口，一個端口表示一個管腳。這種描述方法被稱為結構性描述。One way of describing the function of an entity is to describe how it is composed of sub-components. Each of the sub-components is an instance of some entity, and the interface of the instances are connected together using signals. A signal represents an electrical connection, a wire or a bus. A port map is used to connect signals to the ports of an instantiation, where a port represents a pin. This kind of description is called a structural.另外，也可以用編程語言符號來描述實體的具體功能。這種方法被稱為行為或功能性描述。這種行為性描述使用進程（processes）來實現。每個進程都是同步進行的。進程內的語句按照串行方式運行。Another way of describing the function of an entity is in terms of programming language notations. This is called a behavioural or functional description. The behaviour is described using processes. Each process executes concurrently with respect to all other processes. Statements inside a process execute in sequential order.

配置（Configuration）

配置（configuration）語句用來指定結構體綁定到那個實體上，并且允許改變元件的連接（通過端口映射（port map）和類屬映射（generic map））。

A configuration specifies which architecture is bound to which entity, and it allows to change the component connection (via a port map and generic map).無論設計描述多么復雜，配置語句都是可以省略的。當沒有聲明配置語句時，VHDL為采用標準化的配置。例如，當實體中存在多個相關聯的結構體時，最后一個結構體會自動被編譯器綁定到實體上。Configurations are always optional, no matter how complex the design description. When no configuration has been declared, the VHDL standard specifies a set of rules that provides a default configuration. For example, when an entity has more than one associated architecture, the last architecture compiled will be bound to the entity.