實體（Entity）

一個實體用來描述設計和外部世界的接口。

An entity defines the interface between a design and the outside world.

語法（Syntax）

entity 實例名 is 	[ generic ( 類屬表); ] 	[ port ( 端口表); ]	[ 實例聲明][ begin	并行語句]end [ entity ] [ 實例名]; 
entity entity_name is 	[ generic ( generic_list ); ] 	[ port ( port_list ); ]	[ entity_declarations ][ begin	concurrent_statements ]end [ entity ] [ entity_name ]; 
說明（Description）
一個實例要結合結構體來使用。他們一起用來描述硬件層次塊（一個設計實體）的行為或者結構。一個結構體只能指派給一個實體，但是一個實體可以擁有多個結構體。
An entity is used in combination with an architecture. Together they describe the behaviour or structure of an hierarchical block of hardware (a design entity). The architecture can be assigned to one entity only but one entity may be assigned to multiple architectures.實體定義了設計的名字。另外，實體中定義的類屬可以為設計提供靜態信息（如時間參數或者總線寬度），端口可以為設計和環境之間提供通訊通道。The entity declares the design name. In addition, it defines generics which PRovide static information (like timing parameters or bus width) to a design, and ports which provide communication channels between the design and its environment.實體可以由庫（library）和use語句來事先聲明。這種方式下，所有在一個包（package）中的聲明定義，對所有的實體以及所有指定到實體的結構體可見。The entity declaration may be preceded by the library and use clauses. This way all declarations defined in a package will be visible for the entity and all architectures assigned to it.
示例（Example）
library ieee;use ieee.std_logic_1164.all;  entity BCD_Decoder is  generic (Size: integer := 4);  port (BCD: in std_logic_vector(2 downto 0);        Enable: in std_logic;        LED: out std_ulogic_vector (Size-1 downto 0));   constant Zero: std_ulogic_vector(Size-1 downto 0) := (others => '0');begin  assert (BCD /= "111") report "BCD is 7" severity note;end BCD_Decoder;注釋（Notes）
一個實體可以沒有類屬、端口和語句。實際上，這種用法被用來構建測試程序（testbenches）。It is possible to write an entity without any generics, ports and statements. In fact this is used in constructing testbenches.