元件（Component）

元件聲明了一個(gè)設(shè)計(jì)實(shí)體的虛擬接口，以供元件例化語句使用。

A component declaration declares a virtual design entity interface that may be used in the component instantiation statement.

語法（Syntax）

component component_name [ is ]   [ generic ( generic_list ); ]   [ port ( port_list ); ] end component [ component_name ]; 
component 元件名 [ is ]   [ generic ( 類屬表 ); ]   [ port ( 端口表 ); ] end component [ 元件名 ];
描述（Description）
一個(gè)元件表示一個(gè)實(shí)體/結(jié)構(gòu)體對(duì)。他表示一個(gè)子系統(tǒng)，可以被其他結(jié)構(gòu)體例化來組建一個(gè)多層級(jí)的結(jié)構(gòu)。元件例化類似于一個(gè)板卡上的一個(gè)芯片。
A component rePResents an entity/architecture pair. It specifies a subsystem, which can be instantiated in another architecture leading to a hierarchical specification. Component instantiation is analogous to a chip in a socket in a board.
元件例化前必須聲明。
A component must be declared before it is instantiated.
設(shè)計(jì)實(shí)體和指定元件的綁定可以延后執(zhí)行也可在配置規(guī)范或配置聲明中進(jìn)行。默認(rèn)配置下，元件名必須和他在實(shí)體中使用的名字相同，并且實(shí)體名必須可見。同樣，類屬和端口的名字、模式和類型也必須一致。
The binding of a design entity to a given component may be delayed and may be placed either in the configuration specification or configuration declaration. For default configuration, the component name must match the name of the corresponding entity to be used in its place, and the entity name must be visible. Also generics and ports must match in name, mode and type.
元件可以在包、設(shè)計(jì)實(shí)體、結(jié)構(gòu)體或者塊聲明中定義。如果元件在結(jié)構(gòu)體中聲明，他必須在begin語句前聲明。在這種情況下，元件只能在結(jié)構(gòu)體中使用（例化）。
The component can be defined in a package, design entity, architecture, or block declaration. If the component is declared in an architecture, it must be declared before the begin statement of the architecture. In such a case, the component can be used (instantiated) in the architecture only.
如果元件在包中聲明，那么該元件對(duì)使用該包的所有結(jié)構(gòu)體可見。If a component is declared in a package, then such a component is visible in any architecture, which uses this package.
例程（Example）
component Counter is  generic(N: integer);   port(Clk, Rst, En: in std_logic;        Q: out std_logic_vector(N-1 downto 0)); end component;
注釋（Note）
一個(gè)元件聲明沒有特別定義那個(gè)實(shí)體/結(jié)構(gòu)體對(duì)被綁定到每個(gè)實(shí)例中。如果沒有定義配置聲明或配置規(guī)范，則采用默認(rèn)的綁定。A component declaration does not explicitly define which entity/architecture pair is bound to each instance. If no configuration specification or configuration declaration is defined a default binding is used.