port ( 端口名, ... : [ 模式 ] 數據類型 [ := 設定值 ] );模式 = in | out | inout | buffer | linkage
port ( port_name, ... : [ mode ] data_type [ := ExPRession ] );mode = in | out | inout | buffer | linkage說明（Description）端口表示一個硬件元件的一個管腳或者一組相關聯的管腳。A port represents a pin or a related group of pins on a hardware component.在技術上來說，一個端口就是一個信號。A port is, technically, a signal.五種不同的模式定義如下：The five different modes have the following definitions:in 輸入端口。這種端口只讀。不允許給它賦值。in input port. This port can only be read. It is not allowed to assign a value to it.out 輸出端口。這種端口只能被賦值。不允許讀取它。out output port. This port can only be assigned. It is not allowed to read from it.inout 雙向端口。這種端口既允許讀取亦能賦值。inout bi-directional port. Both assignments to such a port and reading from it are allowed.buffer 帶有讀取功能的輸出端口。它不同于inout的是端口的值僅能由一個源來更新，但是inout的值可以被零或多個源來更新。buffer output port with read capability. It differs from inout in that it can be updated by at most one source, whereas inout can be updated by zero or more sources.linkage。端口的值可以被讀取或者更新，但僅根據與其先關聯的接口模式來實現一個模式。linkage. The value of the port may be read or updated, but only by appearing as an actual corresponding to an interface object of mode linkage.例程（Example）
port (Clk, Rst: in std_logic;D: in std_logic_vector(3 downto 0);Status: out std_logic;Q: buffer std_logic_vector(3 downto 0);注釋（Note）端口定義等同于信號定義，所以端口信號沒必要重復定義。 Port declarations are signal declarations and port signals need not to be re-declared.