數據對象（Data Objects）
數據對象是一個命名項，可以用來表達或存儲數據。每個數據對象都有其數據類型和一組唯一的可能值。他們的值取決于該對象定義的數據類型。 An data object is a named item that can be used to rePResent and store data. Each data object has a specific data type and a unique set of possible values. These values depend on the definition of the data type used for that object.
有以下四種數據對象： There are four different data objects:
常量（Constant）信號（Signal）變量（Variable）共享變量（Shared Variable）常量（Constant）
常量的值一旦在設計中定義就不允許改變。常量可以被顯示聲明，或者被顯示聲明常量的子元素，或者接口常量。在包中定義的常量也可以是延遲常數。 A constant is an object whose value cannot be changed once defined for the design. Constants may be explicitly declared or they may be sub-elements of explicitly declared constants, or interface constants. Constants declared in packages may also be deferred constants.
語法（Syntax）
constant 常量名: 數據類型 [ := 表達式 ]; constant constant_name: data_type [ := expression ];說明（Description）
常量用于給一個值命名，方便讀取和維護代碼。 A constant is used to give a name to a value, this makes it easier to read and maintain the code.
常量聲明的數據類型可能是標準或符合類型，也可被約束。常量不能是文件或者訪問類型。如果常量是一個數組或者記錄，那么其所含元素都不能是文件或訪問類型。 The data type in the constant declaration can be of scalar or composite type and it can be constrained. A constant cannot be of the file or access type. If a constant is an array or a record then none of its elements can be of the file or access type.
常量的可見性取決于他們聲明的位置。包中定義的常量可以被許多設計單元使用。在設計實體中定義的常量對實體的所有語句和結構體本體可見。在設計單元聲明部分定義的常量對和設計相關聯的所有單元可見，包括進程語句。進程中定義的常量進隊該可在該進程中使用。 The visibility of constants depends on the place of their declaration. The constants defined in the package can be used by several design units. The constant declaration in the design entity is seen by all the statements of the architecture bodies of this entity. The constants defined in the declaration part of the design unit is seen in all bodies related to this design, including the process statement. The constant defined in the process can only be used in this process.
例程（Example）
constant Size: Positive := 8; constant MaxSimTime: Time := 200 * ClkPeriod;注釋（Notes）
在仿真進程中不能給常量賦值。A constant may not be assigned any valuess by the simulation process.使用常量定義數據參數和查找表，可以替代函數調用。以這種方式定義的仿真時間查找表可以顯著地縮短函數調用時間。Use constants to define data parameters and lookup tables, which may substitute function calls. The simulation time of such lookup tables is significantly shorter than that of function calls.信號（Signal）
信號是具有上一歷史值得對象。一個信號可以有多個驅動源，每個驅動都有一個當前值和預測的未來值。通過信號聲明和端口聲明來聲明一個信號。 Signal is an object with a past history of values. A signal may have multiple drivers, each with a current value and projected future values. The term signal refers to objects declared by signal declarations and port declarations.
語法（Syntax）
signal 信號名 : 數據類型 [ kind ] [ := 表達式 ]; kind = register | bus -- guarded signalsignal signal_name : data_type [ kind ] [ := expression ]; kind = register | bus -- guarded signal說明（Description）
信號代表了電器連接、連線或總線。信號用來在進程間通信。 A signal represents an electrical connection, wire or bus. Signals are used for communication between processes.
信號可以在以下幾種地方進行聲明： Signals can be explicitly declared in the declarative part of:
包聲明：在包中聲明的信號對使用該包的整個設計實體可見（通過使用use語句）package declaration: signals declared in a package are visible in all design entities using the package (through the use clause).
結構體：結構體聲明的信號僅對結構體可見。
architecture: such signals are visible inside the architecture only.塊：塊中的信號僅限于塊中使用。block: the scope of such signals is limited to the block itself.子程序（函數和程序）：子程序中信號僅對子程序有效。subprogram (function and procedure): the scope of such signals it limited to the subprogram itself.實體中的端口聲明是一種隱式的信號聲明。以這種形式聲明的信號對分配給該實體的所有結構體可見。 A port declaration in an entity is an implicit signal declaration. A signal declared this way is visible in all architectures assigned to that entity.
可以在信號聲明時給他賦初值。如果信號聲明時不包含默認值，則其默認值取決于其左邊的指定類型。綜合時忽略信號的默認值；使用明確的復位來使VHDL和綜合后的硬件進入到一個相同的可知狀態。 A signal can get a default value in its declaration. If the signal declaration does not contain a default value, then the default value of the signal is the left bound of the specified type. The default value is ignored for synthesis; use an explicit reset to get both the VHDL and the synthesized hardware into the same known state.
使用kind語句聲明的信號可以有獨立的驅動源不與其解析函數相連。這種信號必須是解析類型。一個寄存器類型的信號沒有保存其上一值得驅動器。總線類型的信號以來其解析函數來提供一個“非驅動”值。大部分綜合工具忽略解析函數。 A signal declared with a kind statement can have individual drivers disconnected from the resolution function. This signal must be of a resolved type. A register type signal with no drivers connected retains its previous value. The bus type signal relies on the resolution function to supply a “no-drive” value. Most synthesis tools ignore resolution functions.
例程（Example）
signal S1, S2: std_logic_vector(7 downto 0);signal S3: std_ulogic := '0';變量（Variable）
變量在進程中存儲值。 A variable stores a value within a process.
語法（Syntax）
variable 變量名 : 數據類型 [ := 表達式 ]; variable variable_name : data_type [ := expression ];說明（Description）
變量用來在進程和子程序（進程和函數）中存儲信息。變量的值可以在仿真時通過變量賦值語句來改變。 A variable is an object that stores information local to the process and subprogram (procedures and functions) in which it is defined. A variable’s values can be changed during simulation through the variable assignment statements.
變量的定義包含一個或多個標識符，一個（子）類型指示和一個可選的變量初始值。變量可以被聲明為任意可用的類型或子類型，有約束的或者沒有約束的。 A variable declaration includes one or more identifiers, a (sub)type indication and an optional initial value for the variable. A variable can be declared to be of any type or sub type available, either constrained or unconstrained.
進程中聲明的變量在仿真的一開始被賦以初始值。子程序中的變量在子程序調用時都會被初始化一次。 Variables that are declared in processes are initialized with their default values at the start of the simulation. Variables declared in subprograms are initialized each time the subprogram is called.
變量的作用域僅限于其被定義的進程或子程序。共享變量則不一樣，他可以在被許多進程共享。 The scope of variables is limited to the process or subprogram they are defined in. The only exception to this rule is a shared variable, which may be shared by multiple processes.
盡管LRM允許多個進程訪問同一個共享變量，但是沒有定義當多個相沖突的進程訪問同一變量時的情況。這種情況下可能導致不可預料的結果，所以應該避免。 Although the LRM allows several processes to access a single shared variable it does not define what happens when two or more conflicting processes try to access the same variable at the same time. Such a situation may lead to unpredictable results and therefore should be avoided.
例程（Example）
variable V, W: std_logic_vector(7 downto 0);variable X: integer := 5;注釋（Notes）
與信號不同，變量即沒有歷史值也沒有未來值，因為根據其定義，每個變量只有當前值。Unlike signals, variables have neither history nor future, because according to its definition, each variable has only current value. No checking for the last event, time elapsed since the last event, previous value, etc. can be performed on variables.
如果讀取變量值在一個時鐘控制的進程中賦值前，則需要在綜合時為該變量分配一個寄存器。在一個多進程中出現類似情況，則可能需要一些鎖存。
If a value of a variable is read before it is assigned in a clocked process then a register will be synthesized for this variable. A similar situation inside a combinatorial process may lead to generation of a latch.
在子程序中聲明的變量被綜合為組合邏輯。
Variables declared in a subprogram are synthesized as combinatorial logic.共享變量（Shared Variable）
共享變量用于進程間通信。 A shared variable is used to share information between processes.
語法（Syntax）
shared variable 變量名 : 數據類型;shared variable variable_name : data_type;說明（Description）
共享變量可用于進程間通信。可以在結構體中、塊、generate語句和包中聲明。 Shared variables can be used to share information between processes. They may be declared within an architecture, block, generate statement, or package.
共享變量可以被多個進程訪問。但語言上沒有定義如何處理當多個進程同時訪問同一共享變量時的情況。 Shared variables may be accessed by more than one process. However, the language does not define what happens if two or more processes make conflicting accesses to a shared variable at the same time.
例程（Example）
shared variable Count: natural;新聞熱點
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